The present exemplary embodiments relate to the alignment of semiconductor wafers during the stacking of semiconductor wafers and, more particularly, relate to an apparatus and method for the accurate alignment of semiconductor wafers using triangulation.
The packaging density in the electronics industry continuously increases in order to accommodate more electronic devices into a package. In this regard, three-dimensional (3D) wafer-to-wafer stacking technology substantially contributes to the device integration process. Typically, a semiconductor wafer includes several layers of integrated circuitry (e.g., processors, programmable devices, memory devices, wiring, etc.) built on a semiconductor substrate. In order to form a 3D wafer stack, two or more wafer substrates are placed on top of one other and bonded.
3D wafer stacking technology offers a number of potential benefits, including, for example, improved form factors, lower costs, enhanced performance, and greater integration through system-on-chip (SOC) solutions. In addition, the 3D wafer stacking technology may provide other functionality to the chip. For instance, after being formed, the 3D wafer stack may be diced into stacked dies or chips, with each stacked chip having multiple tiers (i.e., layers) of integrated circuitry. SOC architectures formed by 3D wafer stacking can enable high bandwidth connectivity of products such as, for example, logic circuitry and dynamic random access memory (DRAM), that otherwise have incompatible process flows. At present, there are many applications for 3D wafer stacking technology, including high performance processing devices, video and graphics processors, high density and high bandwidth memory chips, and other SOC solutions.
Proper alignment of the semiconductor wafers before bonding is critical to the functionality of 3D interconnected structures. To enable high-density 3D structures, improved accuracy and cost-effective alignment processes are required.
Presently, wafer to wafer alignment for bonding is accomplished through complicated alignment techniques that rely on geometric transpositions of passive structures that represent geometric coordinates on one wafer such that a minimization of alignment error may be accommodated through an external measurement analysis and feedback instrumentation. Instrumentation relies on optical measurement and detection sensors that predominantly operate in the optical and infrared or near infrared range of the electromagnetic spectrum. Multiple sources of error are inherent in this range of the electromagnetic spectrum: such as refraction of image signal due to possible non-optical linearity of the substrate, opacity of substrate due to metal masking layers, intrinsic error in accuracy due to IR wavelength, relative calibration errors in the case of separate optical microscopes, etc.